fvm package

Subpackages

• fvm.drom2psl package
  • Submodules
    • fvm.drom2psl.basiclogging module
      • error()
      • info()
      • warning()
    • fvm.drom2psl.definitions module
      • CONFIG
      • STRETCH
      • STRING
      • TYPE
    • fvm.drom2psl.generator module
      • create_parser()
      • format_arguments_suffix_implication()
      • format_group_arguments()
      • format_group_arguments_in_call()
      • generator()
      • main()
    • fvm.drom2psl.interpret module
      • adapt_value_to_hdltype()
      • assign_datatypes()
      • check_wavelane()
      • classify_value()
      • data2list()
      • exclude_data_types()
      • expand_concatenations()
      • flatten()
      • gen_sere_repetition()
      • get_clock_value()
      • get_group_arguments()
      • get_group_name()
      • get_signal()
      • get_signal_value()
      • get_type()
      • get_wavelane_data()
      • get_wavelane_name()
      • get_wavelane_type()
      • get_wavelane_wave()
      • is_empty()
      • is_pipe()
      • list_elements()
      • list_signal_elements()
      • process_concatenation()
      • process_value()
      • remove_parentheses()
      • remove_psl_operators()
      • split_concatenation()
    • fvm.drom2psl.traverse module
      • traverse()
      • traverse_dict()
      • traverse_edge()
      • traverse_list()
      • traverse_other()
      • traverse_signal()
  • Module contents
• fvm.toolchains package
  • Subpackages
    • fvm.toolchains.questa_pkg package
      • Subpackages
      • Module contents
  • Submodules
    • fvm.toolchains.questa module
      • compile_systemverilog()
      • compile_verilog()
      • compile_vhdl()
      • create_f_file()
      • define_steps()
      • formal_initialize_reset()
      • gen_clock_config()
      • gen_clock_domain_config()
      • gen_reset_config()
      • gen_reset_domain_config()
      • gencompilescript()
      • generics_to_args()
      • get_linecheck_clocks()
      • get_linecheck_common()
      • get_linecheck_friendliness()
      • get_linecheck_lint()
      • get_linecheck_prove()
      • get_linecheck_prove_formalcover()
      • get_linecheck_prove_simcover()
      • get_linecheck_reachability()
      • get_linecheck_resets()
      • get_linecheck_rulecheck()
      • get_linecheck_xverify()
      • get_setup_toplevel()
      • parse_reachability_summary()
      • run_clocks()
      • run_friendliness()
      • run_lint()
      • run_prove()
      • run_prove_formalcover()
      • run_prove_simcover()
      • run_qverify_step()
      • run_reachability()
      • run_resets()
      • run_rulecheck()
      • run_xverify()
      • set_coverage_goal()
      • set_setup_toplevel()
      • set_timeout()
      • setup_clocks()
      • setup_friendliness()
      • setup_lint()
      • setup_prove()
      • setup_prove_formalcover()
      • setup_prove_simcover()
      • setup_reachability()
      • setup_resets()
      • setup_rulecheck()
      • setup_xverify()
      • vhdlstd2flag()
    • fvm.toolchains.toolchains module
      • define_steps()
      • formal_initialize_reset()
      • generics_to_args()
      • get_default_flags()
      • get_linecheck_patterns()
      • get_toolchain()
      • set_coverage_goal()
      • set_timeout()
  • Module contents

Submodules

• fvm.argument_parser module
  • create_parser()
• fvm.framework module
  • FvmFramework
    • FvmFramework.__init__()
    • FvmFramework.add_clock()
    • FvmFramework.add_clock_domain()
    • FvmFramework.add_config()
    • FvmFramework.add_drom_source()
    • FvmFramework.add_drom_sources()
    • FvmFramework.add_psl_source()
    • FvmFramework.add_psl_sources()
    • FvmFramework.add_reset()
    • FvmFramework.add_reset_domain()
    • FvmFramework.add_systemverilog_source()
    • FvmFramework.add_systemverilog_sources()
    • FvmFramework.add_verilog_source()
    • FvmFramework.add_verilog_sources()
    • FvmFramework.add_vhdl_source()
    • FvmFramework.add_vhdl_sources()
    • FvmFramework.allow_failure()
    • FvmFramework.blackbox()
    • FvmFramework.blackbox_instance()
    • FvmFramework.check_errors()
    • FvmFramework.check_tool()
    • FvmFramework.clear_drom_sources()
    • FvmFramework.clear_psl_sources()
    • FvmFramework.clear_systemverilog_sources()
    • FvmFramework.clear_verilog_sources()
    • FvmFramework.clear_vhdl_sources()
    • FvmFramework.cutpoint()
    • FvmFramework.disable_coverage()
    • FvmFramework.exit_if_required()
    • FvmFramework.formal_initialize_reset()
    • FvmFramework.generate_psl_from_drom_sources()
    • FvmFramework.generics_to_args()
    • FvmFramework.get_log_counts()
    • FvmFramework.get_steps()
    • FvmFramework.get_tool_flags()
    • FvmFramework.get_vhdl_std()
    • FvmFramework.init_results()
    • FvmFramework.is_disabled()
    • FvmFramework.is_failure_allowed()
    • FvmFramework.is_skipped()
    • FvmFramework.linecheck()
    • FvmFramework.list_configuration()
    • FvmFramework.list_design()
    • FvmFramework.list_drom_sources()
    • FvmFramework.list_psl_sources()
    • FvmFramework.list_sources()
    • FvmFramework.list_step()
    • FvmFramework.list_systemverilog_sources()
    • FvmFramework.list_verilog_sources()
    • FvmFramework.list_vhdl_sources()
    • FvmFramework.log()
    • FvmFramework.logcheck()
    • FvmFramework.run()
    • FvmFramework.run_cmd()
    • FvmFramework.run_configuration()
    • FvmFramework.run_design()
    • FvmFramework.run_hook()
    • FvmFramework.run_hook_if_defined()
    • FvmFramework.run_post_hook()
    • FvmFramework.run_post_step()
    • FvmFramework.run_pre_hook()
    • FvmFramework.run_step()
    • FvmFramework.set_coverage_goal()
    • FvmFramework.set_logformat()
    • FvmFramework.set_loglevel()
    • FvmFramework.set_post_hook()
    • FvmFramework.set_pre_hook()
    • FvmFramework.set_prefix()
    • FvmFramework.set_timeout()
    • FvmFramework.set_tool_flags()
    • FvmFramework.set_toolchain()
    • FvmFramework.set_toplevel()
    • FvmFramework.set_vhdl_std()
    • FvmFramework.setup_design()
    • FvmFramework.skip()
  • getlogformattool()
• fvm.generate_test_cases module
  • generate_test_case()
  • html_to_oneline()
• fvm.helpers module
  • get_fvm_shortversion()
  • get_fvm_version()
  • getscriptname()
  • insert_line_after_target()
  • insert_line_before_target()
  • is_inside_venv()
  • is_interactive()
  • readable_time()
• fvm.logcounter module
  • LogCounter
    • LogCounter.__init__()
    • LogCounter.get_counts()
• fvm.manage_allure module
  • change_logo()
  • create_parser()
  • download_allure()
  • ensure_allure()
  • extract_allure()
  • get_allure_bin_path()
  • get_allure_dir()
  • get_allure_zip_path()
  • install_allure()
  • main()
  • make_allure_executable()
• fvm.reports module
  • copy_results_to_allure_results()
  • generate_allure()
  • generate_html_report()
  • generate_text_report()
  • generate_xml_report()
  • get_all_steps()
  • pretty_summary()
  • rich_table_to_markdown()
  • show_allure()
• fvm.steps module
  • Steps
    • Steps.__init__()
    • Steps.add_post_step()
    • Steps.add_step()
    • Steps.append_step()
    • Steps.prepend_step()
• fvm.tables module
  • show_coverage_summary()
  • show_friendliness_score()
  • show_prove_summary()
  • show_step_summary()

Module contents

FVM: A Formal Verification Methodology for ASIC and FPGA designs